WiFi access Point ¶ On boot, the board will enable itself as a WiFi access point. PCIe® - Gen2 x1 Endpoint (PS) Gen2 x1 Rootport (PS) - Gen4 x4 Endpoint (PS) Gen2 x4 Rootport (PS) RJ-45 - 1x 1x 1x 1x 1x SFP+ - 2x - 2x 4x This is the second part of a three part tutorial series in which we will create a PCI Express Root Complex design in Vivado with the goal of connecting a PCIe NVMe solid-state drive to our FPGA. by Jeff Johnson | | PCI Express, PicoZed, SSD Storage, Tutorials, Vivado.
This combines quad-core ARM A53 64-bit processors, dual-core R5 32-bit processors, a Mali GPU and Programmable Logic along with WiFi, Bluetooth, and other IO for interfacing. The Ultra96 board provides both developers and makers with a heterogeneous Zynq MPSoC.
